1. Field of the Invention
This invention relates generally to a system for detecting operational faults in a memory device; and, more specifically, relates to a system and method for detecting faults occurring in the addressing logic of storage devices such as General Register Arrays (GRAs).
2. Description of the Prior Art
Many of today""s data processing systems are used in applications that require a high-degree of fault protection. For example, data processing systems now provide the infrastructure that supports everything from modem banking applications, flight control systems, public utilities, and health care facilities. Ensuring that adequate fault detection is available within these systems is of vital importance.
Various techniques have been devised to provide fault detection. For example, data and address signals may be protected using parity codes. Parity codes are generally generated on data and/or address signals at a source point prior to the transmission of the signals. Parity is then re-generated at some destination point, and the re-generated codes are compared to the originally-generated codes to verify that errors have not occurred during signal transmission. This type of system is described in U.S. Pat. No. 5,392,302 to Kemp et al. The disclosed system utilizes gray code counters to generate parity on an address that is to be transferred to a storage array. The parity code is re-generated after the address is transferred to the storage array, and the two codes are compared. If the codes are unequal, an address error is indicated.
While the use of parity codes is generally employed to protect the integrity of data and address paths, this type of error detection is typically not used for control path signal levels. This is due, in part, because unlike address and data signals, control signals generally do not share common source and destination points, and common switching times. This makes generating parity codes on a given set of control signals impractical.
One method of fault detection more commonly used in the protection of control path signal levels involves the use of redundancy. A circuit employing this method of fault detection duplicates critical sections of the logic so that signal levels from the duplicated nets can be compared. If signal levels differ, an error occurred within one of the duplicated logic sections, and fault correction techniques can be applied, if available, to obtain corrected levels. A system employing logic duplication is shown in U.S. Pat. No. 4,233,682 to Liebegot et al. According to this system, duplicate functional logic is employed to implement selected portions of a logic design. Signal levels are compared at key points within the logic to detect both transient and hard failures.
Another system employing redundancy is described in U.S. Pat. No. 5,809,543 to Byers et al., which is assigned to the assignee of the current invention. The disclosed storage system utilizes redundantly stored data signals and redundant data paths and control logic to achieve a fault-tolerant memory complex.
Although the use of redundant logic may be employed to detect faults occurring in control paths, this method may significantly increase the number of circuits required to implement a logic design. For this reason, the use of redundant logic is not a practical means of accomplishing fault detection when space considerations are a priority, and may also be undesirable if power consumption is to be limited. Additionally, the use of redundant logic is not viable when the signals to be verified are included within xe2x80x9coff-theshelfxe2x80x9d logic functions.
Off-the-shelf logic functions may be included within discrete components used in board-level designs, and may also be provided as pre-packaged logic functions that are used in the development of custom and semi-custom silicon device designs. In either instance, the logic included within these pre-packaged logic functions may not be modified by an end user. Thus, the end user may not selectively add redundant logic and compare circuits to implement fault detection.
Memory components are a commonly selected off-the-shelf function. Such components include Random Access Memories (RAMs), Read Only Memories (ROMs), and General Register Arrays (GRAs). These devices may be embodied as discrete components, or as logic functions that are selectively included within a logic design implemented on the die of a custom or semi-custom silicon device. Although the address and data paths associated with these storage devices may be parity protected in the manner discussed above, the internal control circuitry that performs the addressing function is generally not fault protected. This circuitry implements the address decode and enable functions that allow a specific address within the device to be accessed in response to the application of a selected set of address and control signals. A failure within this logic could result in reading from, or writing to, an unexpected addressable location within the memory device. This could cause the retrieval of unexpected data, or may result in data loss.
Because the addressing logic of a storage function is embedded within the off-theshelf logic, selective duplication of this logic is not possible. The addressing function may be fault checked by duplicating the entire device. However, since storage devices generally occupy a significant amount of board space or silicon die area, this is not a desirable solution.
One method of performing fault checking on the internal addressing circuitry of a storage device is described in U.S. Pat. No. 5,768,294 to Chen et al. According to the disclosed system, when data is stored to memory, an Error Correction Code ACC) is also stored that is generated using both the stored data and the address signals. Because the ECC code is calculated using the address signals, a subsequent access to an unexpected address within the storage device will result in an error when the address and data are again used to generate an ECC code that is compared against the originally-stored ECC code. The Chen system is relatively logic intensive, requiring multiple circuits for generating the ECC code, and additional circuits to perform the checking. This is not a practical means for detecting addressing faults in designs in which space limitations are an issue. Additionally, for storage devices that are relatively wide, that is, have a relatively large number of bits per addressable location, the number of ECC bits required to provide fault detection using a system of this type is also relatively large. For example, nine ECC bits are required to provide parity error detection on a group of one hundred and twenty data signals. Thus, within each addressable location, nine additional bits must be provided to store the ECC code. This number of bits may not be available.
What is needed is a system and method for detecting faults in the addressing logic of storage devices that can be employed with off-the-shelf functions, that do not require the duplication of logic circuitry, and that require a minimum number of logic circuits to implement.
The primary object of the invention is to provide an improved fault detection system and method for detecting addressing faults occurring within the addressing logic of storage devices;
A further object of the invention is to provide a fault detection system and method for preventing corrupted data that is parity-correct from penetrating a data processing system;
A further object of the invention is to provide a fault detection system that is capable of detecting addressing faults without the duplication of logic;
A yet further object of the invention is to provide a fault detection system for detecting addressing faults, wherein the system requires a minimum number of logic circuits to implement;
Another object of the invention is to provide a fault detection system for detecting addressing faults, wherein the system requires the use of a minimal number of bits per addressable location to implement the fault detection scheme;
A still further object of the invention is to provide a fault detection system that is particularly adaptable for use with storage devices having a relatively small number of addressable locations, while at the same time having a large number of bits included within each addressable location;
A yet further object of the invention is to provide a fault detection system that can isolate the location of a fault occurring within the addressing logic of a storage device; and
A still further object of the invention is to provide a fault detection system and method that can be employed to detect faults occurring in the addressing logic of off-theshelf storage functions.
These and other more detailed and specific objectives of the invention will become apparent from the following description of the invention.
The objectives of the present invention are achieved in an improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device. When data is stored to a selected address within the storage device, a copy of the address is stored with the data. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the compared addresses are not the same, a potential addressing fault occurred within the control logic of the storage device.
According to one embodiment of the invention, the storage device is a General Register Array (GRA) used as a circular queue. External logic used to address the GRA includes two stored copies of the next GRA address that is to be written. The first copy of this address is used to address the GRA during a write operation, and the second copy of the address provides the address signals that are written to the GRA along with the write data. If a potential address fault is detected when data signals are read from the GRA, the two stored copies of the write address are compared to determine whether the fault is likely caused by a failure in logic that is external to the GRA, or is the result of a failure within the addressing logic of the GRA. In a similar manner, the external logic may maintain two copies of the next GRA address that is to be read. The first copy is used to address the GRA during a read operation, and the second copy is compared against the address signals that are read from the GRA. In the event a potential address fault is detected during this compare operation, the two external copies of the read address may be compared. If the two external address copies do not compare, the fault is likely caused by a failure in the logic external to the GRA, instead of being caused by addressing logic within the GRA itself Still other objects and advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description of the preferred embodiment and the drawings, wherein only the preferred embodiment of the invention is shown, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded to the extent of applicable law as illustrative in nature and not as restrictive.